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| xr JULY 2005 PRELIMINARY XRT91L80 REV. P1.1.0 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER GENERAL DESCRIPTION The XRT91L80 is a fully integrated SONET/SDH transceiver for SONET OC-48/STM-16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the highspeed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) functions by synchronizing its onchip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serialto-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the FIGURE 1. BLOCK DIAGRAM OF XRT91L80 control of the FIFO_AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU, LOCKDET_CDR, and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS * SONET/SDH-based Transmission Systems * Add/Drop Multiplexers * Cross Connect Equipment * ATM and Multi-Service Switches and Routers * DSLAMS * SONET/SDH Test Equipment * DWDM Termination Equipment STS-48 TRANSCEIVER FIFO_RST FIFO_AUTORST TXDI0P/N TXDI1P/N TXDI2P/N TXDI3P/N TXPCLKIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16DIS Div by 4 Div by 16 WP 4x9 FIFO PISO (Parallel Input Serial Output) TXOP/N Re-Timer RP CMU DLOOP RLOOPS RLOOPP RXDO0P/N RXDO1P/N RXDO2P/N RXDO3P/N RXPCLKOP/N RXCLKO16P/N Div by 4 Div by 16 SIPO (Serial Input Parallel Output) CDR RXIP/N DISRD LOSDMUTE TDO TDI TCK TMS TRST JTAG Serial Microprocessor Hardware Control PFD & Charge Pump RLOOPS RLOOPP DLOOP LOOPTM_JA LOOPTM_NOJA LOOPBW LOCKDET_CMU LOCKDET_CDR LOSDET SDEXT POLARITY TEST Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com REFCLKP/N VCXO_INP/N ALTFREQSEL VCXO_SEL VCXO_LOCKEN VCXO_LOCK CPOUT OVERFLOW CS SCLK SDI SDO HOST/HW INT RESET XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER FEATURES xr REV. P1.1.0 * 2.488 / 2.666 Gbps Transceiver * Targeted for SONET OC-48/SDH STM-16 Applications * Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps * Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, and clock data recovery (CDR) functions * 4-bit LVDS signaling data paths running at 622.08/666.51 Mbps compliant with OIF SFI-4 Implimentation Agreement * Non-FEC and FEC rate REFCLKP/N single reference input port * Supports 77.76/83.31 MHz or 155.52/166.63 MHz transmit and receive external reference input port * Optional VCXO input port support multiple de-jittering modes * On-chip phase detector and charge pump for external VCXO based de-jittering PLL * Internal FIFO decouples transmit parallel clock input and transmit parallel clock output * Provides Local, Remote Serial, Remote Parallel and Split Loopback modes as well as Loop Timing mode * Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect * Host mode serial microprocessor interface simplifies monitor and control * Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, GR-253 CORE, GR-253 ILR SONET Jitter specifications. * Operates at 1.8V CMOS and CML with 3.3V I/O * 490mW Typical Power Dissipation * Package: 12 x 12 mm 196-pin STBGA * IEEE 1149.1 Compatable JTAG port PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRT91L80IB PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40 to +85 C C 2 REV. P1.1.0 xr xr xr xr FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW) A AGND_RX TRST LOSDMUTE NC DGND RXCLKO16P RXCLKO16N VDD3.3 SDI CS RLOOPP DGND VDD1.8 RXDO3P B AGND_RX AGND_RX DGND NC SDEXT DLOOP VDD1.8 DGND SCLK RESET TDO DGND VDD1.8 RXDO3N C RXIP AGND_RX AGND_RX POLARITY LOSDET LOOPTM_JA LOCKDET_CDR SDO HOST/HW RLOOPS INT DISRD RXDO2P RXDO1P D RXIN AGND_RX AVDD3.3_RX AVDD1.8_RX AVDD1.8_RX AVDD1.8_RX AGND_RX AVDD1.8_RX VDD3.3 VDD3.3 VDD3.3 VDD1.8 RXDO2N RXDO1N E AGND_RX AGND_RX AVDD3.3_RX AGND_RX TGND TGND TGND TGND TGND TGND VDD3.3 VDD1.8 RXDO0P RXPCLKOP F XRES1N AGND_RX AVDD1.8_RX AGND_RX TGND TGND TGND TGND TGND TGND DGND DGND RXDO0N RXPCLKON PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER G XRES1P AGND_RX AVDD1.8_RX AGND_RX TGND TGND TGND TGND TGND TGND DGND DGND DGND DGND H AGND_RX AGND_RX AGND_RX AGND_RX TGND TGND TGND TGND TGND TGND DGND DGND TXDI0P TXPCLKIP 3 J AVDD1.8_TX AGND_TX AGND_TX AVDD1.8_TX TGND TGND TGND TGND TGND TGND DGND DGND TXDI0N TXPCLKIN K TXOP AGND_TX AGND_TX AGND_TX TGND TGND TGND TGND TGND TGND VDD1.8 DGND TXDI2P TXDI1P L TXON AGND_TX DGND AGND_TX AGND_TX AVDD1.8_TX AVDD1.8_TX AVDD1.8_TX VDD1.8 VDD1.8 DGND DGND TXDI2N TXDI1N M AGND_TX AVDD1.8_TX AVDD1.8_TX AGND_TX AGND_TX VCXO_SEL LOOPBW TDI VDD1.8 VDD1.8 VDD1.8 TXCLKO16DIS OVERFLOW TXDI3P N TMS LOCKDET_CMU TCK VCXO_INN AGND_TX REFCLKN AGND_TX VCXO_LOCK AVDD1.8_TX TXCLKO16PTXCLKO16N FIFO_AUTORST FIFO_RST TXDI3N P ALTFREQSEL LOOPTM_NOJA VCXO_LOCKEN VCXO_INP AVDD3.3_TX REFCLKP AGND_TX CPOUT AVDD3.3_TX TXPCLKOP TXPCLKON DGND VDD3.3 VDD3.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.1.0 TABLE OF CONTENTS GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ...........................................................................................................................................1 FIGURE 1. BLOCK DIAGRAM OF XRT91L80 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 PRODUCT ORDERING INFORMATION ..................................................................................................2 FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW).......................................................................................................... 3 TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS ..........................................................................................................4 SERIAL MICROPROCESSOR INTERFACE............................................................................................................4 HARDWARE COMMON CONTROL ......................................................................................................................5 TRANSMITTER SECTION ..................................................................................................................................6 RECEIVER SECTION.........................................................................................................................................9 POWER AND GROUND ..................................................................................................................................10 NO CONNECTS.............................................................................................................................................11 JTAG ..........................................................................................................................................................12 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................13 1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 13 1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 13 TABLE 1: REFERENCE FREQUENCY OPTIONS (NON-FEC AND FEC MODE)...................................................................................... 13 1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 13 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 13 2.0 RECEIVE SECTION .............................................................................................................................14 2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14 FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 14 TABLE 2: DIFFERENTIAL CML INPUT SWING PARAMETERS .............................................................................................................. 14 2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15 TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 15 2.3 EXTERNAL SIGNAL DETECTION ................................................................................................................. 15 TABLE 4: LOSD DECLARATION POLARITY SETTING ......................................................................................................................... 16 2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 16 FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 16 2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 16 FIGURE 6. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 16 2.6 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 17 FIGURE 7. LVDS EXTERNAL BIASING RESISTORS............................................................................................................................. 17 2.7 PARALLEL RECEIVE DATA OUTPUT MUTE UPON LOSD ........................................................................ 17 2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE ......................................................................................... 17 2.9 RECEIVE PARALLEL DATA OUTPUT TIMING ............................................................................................ 17 FIGURE 8. RECEIVE PARALLEL OUTPUT TIMING .............................................................................................................................. 17 TABLE 5: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS ........................................................................... 17 3.0 TRANSMIT SECTION ..........................................................................................................................18 3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 18 FIGURE 9. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................... 18 3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 19 FIGURE 10. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 19 TABLE 6: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION............................................................................... 19 TABLE 7: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION ........................................................................................... 19 3.3 TRANSMIT FIFO ............................................................................................................................................. 19 FIGURE 11. TRANSMIT FIFO AND SYSTEM INTERFACE .................................................................................................................... 20 3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 20 3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 20 FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 20 3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 21 TABLE 8: CLOCK MULTIPLIER UNIT PERFORMANCE ......................................................................................................................... 21 3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 21 TABLE 9: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS .............................................................................................. 22 FIGURE 13. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO.......................................................................................... 22 3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 23 I xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER FIGURE 14. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 23 3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 23 FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 23 4.0 DIAGNOSTIC FEATURES ................................................................................................................... 24 4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 24 FIGURE 16. SERIAL REMOTE LOOPBACK......................................................................................................................................... 24 4.2 PARALLEL REMOTE LOOPBACK ............................................................................................................... 24 FIGURE 17. PARALLEL REMOTE LOOPBACK .................................................................................................................................... 24 4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 25 FIGURE 18. DIGITAL LOOPBACK...................................................................................................................................................... 25 4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 26 4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 26 FIGURE 19. JITTER TOLERANCE MASK............................................................................................................................................ 26 FIGURE 20. 91L80 MEASURED JITTER TOLERANCE WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS48.................................................................................................................................................................................. 27 4.4.2 JITTER TRANSFER .................................................................................................................................................... 27 FIGURE 21. 91L80 MEASURED JITTER TRANSFER WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS48.................................................................................................................................................................................. 27 4.4.3 JITTER GENERATION................................................................................................................................................ 28 FIGURE 22. 91L80 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS...................................... 28 FIGURE 23. 91L80 MEASURED ELECTRICAL PHASE NOISE RECEIVE JITTER GENERATION AT 2.488 GBPS........................................ 28 5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 29 FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 29 5.1 SERIAL TIMING INFORMATION ................................................................................................................... 29 FIGURE 25. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 29 5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 30 5.2.1 5.2.2 5.2.3 5.2.4 R/W (SCLK1)............................................................................................................................................................... A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. X (DUMMY BIT SCLK8) .............................................................................................................................................. D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 30 30 30 30 5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 30 6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 31 TABLE 10: TABLE 11: TABLE 12: TABLE 13: TABLE 14: TABLE 15: TABLE 16: TABLE 17: TABLE 18: MICROPROCESSOR REGISTER MAP................................................................................................................................ 31 MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 31 MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 32 MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 32 MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 33 MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 35 MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 35 MICROPROCESSOR REGISTER 0X3EH BIT DESCRIPTION ................................................................................................. 37 MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION ................................................................................................. 37 7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 38 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 38 POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 38 ................................................................................................................................................................... 39 COMMON MODE LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................ 39 ................................................................................................................................................................... 39 LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 39 LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 40 LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ........................................................... 40 ORDERING INFORMATION .................................................................................................................. 41 REVISION HISTORY ...................................................................................................................................... 42 II XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.1.0 PIN DESCRIPTIONS SERIAL MICROPROCESSOR INTERFACE NAME HOST/HW LEVEL LVTTL, LVCMOS TYPE I PIN C9 DESCRIPTION Host or Hardware Mode Select Input The XRT91L80 offers two modes of operation for interfacing to the device. The Host mode uses a serial microprocessor interface for programming individual registers. The Hardware mode is controlled by the state of the hardware pins set by the user. When left unconnected, by default, the device is configured in the Hardware mode. "Low" = Hardware Mode "High" = Host Mode This pin is provided with an internal pull-down. Chip Select Input (Host Mode Only) Active "Low" signal. This signal enables the serial microprocessor interface by pulling chip select "Low". The serial microprocessor is disabled when the chip select signal returns "High". NOTE: The serial microprocessor interface does not support burst mode. Chip Select must be de-asserted after each operation cycle. This pin is provided with an internal pull-up. SCLK LVTTL, LVCMOS I B9 Serial Clock Input (Host Mode Only) Once CS is pulled "Low", the serial microprocessor interface requires 16 clock cycles for a complete Read or Write operation. This pin is provided with an internal pull-down. Serial Data Input (Host Mode Only) When CS is pulled "Low", the serial data input is sampled on the rising edge of SCLK. This pin is provided with an internal pull-down. Serial Data Output (Host Mode Only) If a Read function is initiated, the serial data output is updated on the falling edge of SCLK8 through SCLK15, with the LSB (D0) updated first. This enables the data to be sampled on the rising edge of SCLK9 through SCLK16. Interrupt Output (Host Mode Only) Active "Low" signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". NOTE: This pin requires an external pull-up resistor. RESET LVTTL, LVCMOS I B10 Master Reset Input Active "Low" signal. When this pin is pulled "Low" for more than 10S, the internal registers are set to their default state. See the register description for the default values. This pin is provided with an internal pull-up. CS LVTTL, LVCMOS I A10 SDI LVTTL, LVCMOS I A9 SDO LVCMOS O C8 INT LVCMOS O C11 4 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER LEVEL LVTTL, LVCMOS TYPE I PIN C10 DESCRIPTION Serial Remote Loopback The serial remote loopback mode interconnects the receive serial data input to the transmit serial data output. If serial remote loopback is enabled, the 4-bit parallel transmit data input is ignored while the 4-bit parallel receive data output is maintained. "Low" = Disabled "High" = Serial Remote Loopback Mode Enabled NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature. This pin is provided with an internal pull-down. HARDWARE COMMON CONTROL NAME RLOOPS RLOOPP LVTTL, LVCMOS I A11 Parallel Remote Loopback The parallel remote loopback mode allows the serial data input stream to pass through the clock and data recovery circuit and looped-back at the parallel interface to the serial output port. The 4-bit parallel transmit data input is ignored while the 4-bit parallel receive data output is maintained. "Low" = Disabled "High" = Parallel Remote Loopback Mode Enabled NOTE: DLOOP and RLOOPS should be disabled when RLOOPP is enabled. The internal FIFO should also be flushed using FIFO_RST pin or register bit when parallel remote loopback is enabled/disabled. This pin is provided with an internal pull-down. DLOOP LVTTL, LVCMOS I B6 Digital Local Loopback The digital local loopback mode interconnects the 4-bit parallel transmit data and parallel transmit clock input to the 4-bit parallel receive data and parallel receive clock output respectively while maintaining the transmit serial data output. If digital local loopback is enabled, the receive serial data input is ignored. "Low" = Disabled "High" = Digital Local Loopback Mode Enabled NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature. This pin is provided with an internal pull-down. 5 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER HARDWARE COMMON CONTROL NAME LOOPTM_JA LEVEL LVTTL, LVCMOS TYPE I PIN C6 DESCRIPTION xr REV. P1.1.0 Loop Timing Mode With Jitter Attenuation The LOOPTM_JA pin must be set "High" in order to select the recovered receive clock as the reference source for the de-jitter PLL. "Low" = Disabled "High" = Loop timing with de-jitter PLL Activated This pin is provided with an internal pull-down. Loop Timing Mode With No Jitter Attenuation When the loop timing mode is activated, the external local reference clock input to the CMU is replaced with the 1/16th or 1/ 32nd of the high-speed recovered receive clock coming from the CDR. "Low" = Disabled "High" = Loop timing Activated This pin is provided with an internal pull-down. LOOPTM_NOJA LVTTL, LVCMOS I P2 TRANSMITTER SECTION NAME TXDI0P TXDI0N TXDI1P TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N TXPCLKIP TXPCLKIN LEVEL LVDS TYPE I PIN H13 J13 K14 L14 K13 L13 M14 N14 H14 J14 DESCRIPTION Transmit Parallel Data Input The 622.08 Mbps 4-bit parallel transmit data input should be applied to the transmit parallel bus simultaneously to be sampled at the rising edge of the TXPCLKIP/N input. The 4-bit parallel interface is multiplexed into the transmit serial output interface MSB first (TXDI3P/N). NOTE: The XRT91L80 can accept 666.51 Mbps 4-bit parallel transmit data input for Forward Error Correction (FEC) Applications. Transmit Parallel Clock Input 622.08 MHz clock input used to sample the 4-bit parallel transmit data input TXDI[3:0]P/N. NOTE: The XRT91L80 can accept a 666.51 MHz transmit clock input for Forward Error Correction (FEC) Applications. TXOP TXON CMLDIFF O K1 L1 Transmit Serial Data Output The transmit serial data output stream is generated by multiplexing the 4-bit parallel transmit data input into a 2.488 Gbps serial data output stream. In Forward Error Correction, the transmit serial data output stream is 2.666 Gbps. Reference Clock Input This differential clock input reference is used for the transmit clock multiplier unit (CMU) to provide the necessary high-speed clock reference for this device. Pin ALTFREQSEL determines the value used as the reference. See Pin ALTFREQSEL for more details. Voltage Controled Oscillator Input This differential clock input is used for the transmit PLL jitter attenuation. Pin ALTFREQSEL determines the value used as the reference. See Pin ALTFREQSEL for more details. LVDS I REFCLKP REFCLKN LVPECL I P6 N6 VCXO_INP VCXO_INN LVPECL I P4 N4 6 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER LEVEL LVTTL, LVCMOS TYPE I PIN P1 DESCRIPTION Reference Clock Frequency Select This pin is used to select the frequency of the REFCLKP/N clock input to the CMU. "Low" = 77.76 MHz (83.31 MHz for FEC) "High" = 155.52 MHz (166.63 MHz for FEC) This pin is provided with an internal pull-up. De-Jitter VCXO Select Option This pin selects either the normal REFCLKP/N or the de-jitter VCXO_INP/N pin as a reference clock to the CMU. "Low" = Normal REFCLKP/N reference clock "High" = De-Jitter VCXO_INP/N reference clock This pin is provided with an internal pull-down. De-Jitter PLL Lock Detect If the de-jitter PLL lock detect is enabled with pin P3 and the dejitter VCXO mode is selected by pin M6, this pin will assert "High" when the PLL is locked. "Low" = VCXO Out of Lock "High" = VCXO Locked De-Jitter PLL Lock Detect Enable This pin enables the VCXO_INP/N lock detect circuit and VCXO_LOCK pin N8 to be active. "Low" = VCXO Lock Detect Disabled "High" = VCXO Lock Detect Enabled This pin is provided with an internal pull-down. Charge Pump Output (for external VCXO) The nominal output of the charge pump current is 250A CMU Loop Bandwidth Select This pin is used to select the bandwidth of the clock multiplier unit of the transmit path to a narrow or wide band. Use Wide Band for clean reference signals and Narrow Band for noisy references. "Low" = Wide Band (4x) "High" = Narrow Band (1x) This pin is provided with an internal pull-down. Transmit Parallel Clock Output This 622.08 MHz clock can be used for the downstream device to generate the TXDI[3:0]P/N data and TXPCLKIP/N clock input. This enables the downstream device and the STS-48/ STM-16 transceiver to be in synchronization. NOTE: The XRT91L80 can output a 666.51 MHz transmit clock output for Forward Error Correction (FEC). TRANSMITTER SECTION NAME ALTFREQSEL VCXO_SEL LVTTL, LVCMOS I M6 VCXO_LOCK LVCMOS O N8 VCXO_LOCKEN LVTTL, LVCMOS I P3 CPOUT - O P8 LOOPBW LVTTL, LVCMOS I M7 TXPCLKOP TXPCLKON LVDS O P10 P11 7 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TRANSMITTER SECTION NAME TXCLKO16P TXCLKO16N LEVEL LVDS TYPE O PIN N10 N11 DESCRIPTION xr REV. P1.1.0 Auxiliary Clock Output (155.52/166.63 MHz) 155.52/166.63 MHz auxiliary clock derived from CMU output. This clock can also be used for the downstream device as a reference for generating the TXDI[3:0]P/N data and TXPCLKIP/N clock input. This enables the downstream device and the STS48/STM-16 transceiver to be in synchronization. The output of this pin is controlled by TXCLKO16DIS. Auxiliary Clock Disable This pin is used to control the activity of the auxiliary clock. "Low" = TXCLKO16P/N Enabled "High" = TXCLKO16P/N Disabled This pin is provided with an internal pull-down. CMU Lock Detect This pin is used to monitor the lock condition of the clock multiplier unit. "Low" = CMU Out of Lock "High" = CMU Locked Transmit FIFO Overflow This pin is used to monitor the transmit FIFO status. "Low" = Normal Status "High" = Overflow Condition FIFO Control Reset FIFO_RST should be held "High" for a minimum of 2 TXPCLKOP/N cycles after powering up and during manual FIFO reset. After the FIFO_RST pin is returned "Low," it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an interrupt indication that the FIFO has an overflow condition, this pin is used to reset or flush out the FIFO. "Low" = Normal Operation "High" = Manual FIFO Reset NOTE: To automatically reset the FIFO, see FIFO_AUTORST pin. This pin is provided with an internal pull-down. TXCLKO16DIS LVTTL, LVCMOS I M12 LOCKDET_CMU LVCMOS O N2 OVERFLOW LVCMOS O M13 FIFO_RST LVTTL, LVCMOS I N13 FIFO_AUTORST LVTTL, LVCMOS I N12 Automatic FIFO Overflow Reset If this pin is set "High", the STS-48/STM-16 transceiver will automatically flush the FIFO upon an overflow condition. Upon power-up, the FIFO should be manually reset by setting FIFO_RST "High" for a minimum of 2 TXPCLKOP/N cycles. "Low" = Manual FIFO reset required for Overflow Conditions "High" = Automatically resets FIFO upon Overflow Detection This pin is provided with an internal pull-down. 8 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER LEVEL LVDS TYPE O PIN E13 F13 C14 D14 C13 D13 A14 B14 E14 F14 DESCRIPTION Receive Parallel Data Output 622Mbps 4-bit parallel receive data output is updated simultaneously on the rising edge of the RXPCLKOP/N output. The 4bit parallel interface is de-multiplexed from the receive serial data input MSB first (RXDO3P/N). NOTE: The XRT91L80 can output 666.51 Mbps 4-bit parallel receive data output for Forward Error Correction (FEC) Applications. Receive Parallel Clock Output 622.08 MHz parallel clock output used to update the 4-bit parallel receive data output RXDO[3:0]P/N at the rising edge of this clock.. NOTE: The XRT91L80 can output a 666.51 MHz receive clock output for Forward Error Correction (FEC). RECEIVER SECTION NAME RXDO0P RXDO0N RXDO1P RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N RXPCLKOP RXPCLKON LVDS O DISRD LVTTL LVCMOS I C12 Parallel Receive Data Output Disable This pin is used to disable the RXDO[3:0]P/N parallel receive data output bus asynchronously. "Low" = Normal Mode "High" = Forces RXDO[3:0]P/N to a logic state "0" This pin is provided with an internal pull-down. Receive Serial Data Input The receive serial data stream of 2.488 Gbps is applied to these input pins. In Forward Error Correction, the receive serial data stream is 2.666 Gbps. External LVDS Biasing Resistors A 402 resistor with +/-1% tolerance should be placed across these 2 pins for proper biasing. Auxiliary Clock Output (155.52/166.63 MHz) 155.52/166.63 MHz auxiliary clock derived from divide-by-16 CDR recovered clock. CDR Lock Detect This pin is used to monitor the lock condition of the clock and data recovery unit. "Low" = CDR Out of Lock "High" = CDR Locked Signal Detect Input from Optical Module Hardware Mode When inactive, it will immediately declare a Loss of Signal Detect (LOSD) condition and assert LOSDET output pin and control the activity of the RXDO[3:0]P/N parallel data output based on LOSDMUTE pin setting. Host Mode In addition to asserting LOSDET output pin, it will update the LOSD condition on the registers and control the activity of the RXDO[3:0]P/N parallel data output based on LOSDMUTE register bit setting. "Active" = Normal Operation "Inactive" = LOSD Condition (SDEXT detects signal absence) This pin is provided with an internal pull-down. RXIP RXIN CMLDIFF I C1 D1 XRES1P XRES1N RXCLKO16P RXCLKO16N LOCKDET_CDR - I G1 F1 A6 A7 C7 LVDS O LVCMOS O SDEXT LVTTL, LVCMOS I B5 9 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION NAME POLARITY LEVEL LVTTL, LVCMOS TYPE I PIN C4 DESCRIPTION xr REV. P1.1.0 Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "Low" = SDEXT is active "Low." "High" = SDEXT is active "High." This pin is provided with an internal pull-down. LOS Detect Condition Flags LOSD condition based on SDEXT signal coming from the optical module. "Low" = No Alarm "High" = A LOS condition is present Parallel Receive Data Output Mute Upon LOSD If this pin is asserted "High", the receive data output will automatically be forced to a logic state of "0" when an LOSD condition occurs. "Low" = Disabled "High" = Mute RXDO[3:0]P/N Data Upon LOSD Condition This pin is provided with an internal pull-down. LOSDET LVCMOS O C5 LOSDMUTE LVTTL, LVCMOS I A3 POWER AND GROUND NAME VDD3.3 TYPE PWR PIN A8, D9, D10, D11, E11, P13, P14 DESCRIPTION CMOS Digital 3.3V I/O Power Supply VDD3.3 should be isolated from the analog power supplies. For best results, use a ferrite bead along with an internal power plane separation. The VDD3.3 power supply pins should have bypass capacitors to the nearest ground. Analog 3.3V I/O Receiver Power Supply AVDD3.3_RX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD3.3_RX power supply pins should have bypass capacitors to the nearest ground. Analog 3.3V I/O Transmitter Power Supply AVDD3.3_TX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD3.3_TX power supply pins should have bypass capacitors to the nearest ground. CMOS Digital 1.8V Core Power Supply VDD1.8 should be isolated from the analog power supplies. For best results, use a ferrite bead along with an internal power plane separation. The VDD1.8 power supply pins should have bypass capacitors to the nearest ground. Analog 1.8V Core Receiver Power Supply AVDD1.8_RX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD1.8_RX power supply pins should have bypass capacitors to the nearest ground. AVDD3.3_RX PWR D3, E3 AVDD3.3_TX PWR P5, P9 VDD1.8 PWR A13, B7, B13, D12, E12, K11, L9, L10, M9, M10, M11 AVDD1.8_RX PWR D4, D5, D6, D8, F3, G3 10 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER PIN J1, J4, L6, L7, L8, M3, N9, M2 DESCRIPTION Analog 1.8V Core Transmitter Power Supply AVDD1.8_TX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD1.8_TX power supply pins should have bypass capacitors to the nearest ground. Digital Ground for 3.3V I/O and 1.8V Core Digital Power Supplies It is recommended that all ground pins of this device be tied together. Receiver Analog Ground for 3.3V I/O and 1.8V Core Analog Power Supplies It is recommended that all ground pins of this device be tied together. POWER AND GROUND NAME AVDD1.8_TX TYPE PWR DGND GND A5, A12, B3, B8, B12, F11, F12, G11, G12, G13, G14, H11, H12, J11, J12, K12, L3, L11, L12, P12 A1, B1, B2, C2, C3, D2, D7, E1, E2, E4, F2, F4, G2, G4, H1, H2, H3, H4 AGND_RX GND AGND_TX GND J2, J3, K2, K3, K4, L2, L4, Transmitter Analog Ground for 3.3V I/O and 1.8V Core L5, M1, M4, M5, N5, N7, Analog Power Supplies P7 It is recommended that all ground pins of this device be tied together. E5, E6, E7, E8, E9, E10, Thermal Ground F5, F6, F7, F8, F9, F10, It is recommended that all ground pins of this device be tied G5, G6, G7, G8, G9, G10, together. H5, H6, H7, H8, H9, H10, J5, J6, J7, J8, J9, J10, K5, K6, K7, K8, K9, K10 TGND GND NO CONNECTS NAME NC LEVEL TYPE NC PIN A4 B4 DESCRIPTION No Connect This pin can be left floating or tied to ground. 11 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JTAG SIGNAL NAME TCK TMS PIN # N3 N1 TYPE I I DESCRIPTION Test clock: Boundary Scan Clock Input. xr REV. P1.1.0 Test Mode Select: Boundary Scan Mode Select Input. JTAG is disabled by default. Note: This input pin should be pulled "Low" for JTAG operation This pin is provided with an internal pull-up. Test Data In: Boundary Scan Test Data Input This pin is provided with an internal pull-up. Test Data Out: Boundary Scan Test Data Output JTAG Test Reset Input Note: This input pin should be pulled "Low" to reset JTAG This pin is provided with an internal pull-up. TDI TDO TRST M8 B11 A2 I O I 12 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 1.0 FUNCTIONAL DESCRIPTION The XRT91L80 transceiver is designed to operate with a SONET Framer/ASIC device and provide a highspeed serial interface to optical networks. The transceiver converts 4-bit parallel data at 622.08/666.51 Mbps to a serial CML bit stream at 2.488/2.666 Gbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-serialization (SerDes), and receive clock and data recovery (CDR) unit. The transceiver is divided into transmit and receive sections and is used to provide the front end component of SONET equipment, which includes primarily serial transmit and receive functions. 1.1 Hardware Mode vs. Host Mode Functionality of the STS-48/STM-16 transceiver can be configured by using either Host mode or Hardware mode. If Hardware mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected, the functionality is controlled by the hardware pins described in the Hardware Pin Descriptions. However, if Host mode is selected by pulling HOST/HW "High", the functionality is controlled by programming internal R/W registers using the Serial Microprocessor interface. Whether using Host or Hardware mode, the functionality remains the same. Therefore, the following sections describe the functionality rather than how each function is controlled. The Hardware Pin Descriptions and the Register Bit Descriptions concentrate on configuring the device. 1.2 Clock Input Reference The XRT91L80 can accept either a 77.76/83.3 MHz or 155.52/166.63 MHz clock input at REFCLKP/N as its internal timing reference for generating higher speed clocks. The reference clock can be provided with one of two frequencies chosen by ALTFREQSEL. The reference frequency options for the XRT91L80 are listed in Table 1. TABLE 1: REFERENCE FREQUENCY OPTIONS (NON-FEC AND FEC MODE) ALTFREQSEL 0 1 REFERENCE CLOCK FREQUENCY 77.76/83.3 MHz 155.52/166.63 MHz TRANSMIT/RECEIVE DATA RATE 2.488/2.666 Gbps 2.488/2.666 Gbps OPERATING MODE STS-48/STM-16 STS-48/STM-16 1.3 Forward Error Correction (FEC) Forward Error Correction is used to control errors along a one-way path of communication. FEC sends extra information along with data which can be used by a receiver to check and correct the data without requesting re-transmission of the original information. It does so by introducing a known structure into a data sequence prior to transmission. The most common methods are to replace a 14-bit data packet with a 15-bit codeword structure, or to replace a 17-bit data packet with an 18-bit codeword structure. To maintain original bandwidth, a higher speed clock reference, derived by the ratio of 15/14 or 18/17 referenced to 77.76MHz or 155.52MHz is applied to the STS-48/STM-16 transceiver using an external crystal. The XRT91L80 supports FEC by accepting a clock input reference frequency of 83.31 MHz or 166.63 MHz. This allows the transmit 4-bit parallel data input to be applied to the STS-48/STM-16 transceiver at 666.51 Mbps which is converted to a 2.666 Gbps serial output stream to an optical module. A simplified block diagram of FEC is shown in Figure 3. FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION FEC codec SONET/Framer ASIC STS-48 Transceiver Optical Module Optical Module STS-48 Transceiver FEC codec Optical Fiber SONET/Framer ASIC 13 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.0 RECEIVE SECTION xr REV. P1.1.0 The receive section of XRT91L80 includes the differential inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter (SIPO). The receiver accepts the high speed NonReturn to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential input interfaces RXIP/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered serial data is converted into 4-bit-wide 622.08/666.51 Mbps parallel data and presented to the RXD[3:0]P/N LVDS parallel interface. A divide-by-4 version of the high-speed recovered clock, RXPCLKOP/N, is used to synchronize the transfer of the 4-bit RXDO[3:0]P/N data with the receive portion of the upstream device. Upon initialization or loss of signal or loss of lock the 77.76/155.52 MHz (83.31/166.63 MHz) external local reference clock is used to start-up the clock recovery phase-locked loop for proper operation. A special loop-back feature can be configured when parallel remote loopback (RLOOPP) is used in conjunction with de-jittered loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore jitter generation specifications. 2.1 Receive Serial Input The receive serial CML inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an optical module or an electrical interface. A simplified AC coupled block diagram is shown in Figure 4. FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK 0.1F RXIP RXIN 0.1F XRT91L80 STS-48/ STM-16 Transceiver Optical Module Optical Fiber NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors are not necessary and can be excluded. The 2.488/2.666 Gbps high-speed differential CML RXIP/N input swing characteristics is shown in Table 2. TABLE 2: DIFFERENTIAL CML INPUT SWING PARAMETERS PARAMETER VINDIFF VINSE VINBIAS RDIFF DESCRIPTION Differential Input Voltage Swing Single-Ended Input Voltage Swing Input Bias Range (AC Coupled) Differential Input Resistance MIN 200 100 1.0 75 TYP MAX 1000 600 1.4 125 UNITS mV mV V 14 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.2 Receive Clock and Data Recovery The clock and data recovery unit accepts the high speed NRZ serial data from the differential CML receiver and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes the REFCLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the local reference clock within 500 ppm. Once this is achieved, the PLL then attempts to lock onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock. When this condition occurs the PLL will declare Loss of Lock and the LOCKDET_CDR signal will be pulled "Low." Whenever a Loss of Lock/Loss of Signal Detection (LOSD) event occurs, the CDR will continue to supply a receive clock (based on the local reference clock) to the upstream framer device. A Loss of Lock condition will also be declared when the external SDEXT becomes inactive. When the SDEXT is de-asserted by the optical module and LOSDMUTE is enabled, receive parallel data output will be forced to a logic zero state for the entire duration that a LOSD condition is detected. This acts as a receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming data. When SDEXT becomes active and the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source, the clock recovery PLL will switch and lock back onto the incoming receive data stream and the lock detect output (LOCKDET_CDR) will go active. Table 3 specifies the Clock and Data Recovery Unit performance characteristics. TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE NAME REFDUTY REFTOL OCLKJIT OCLKJIT TOLJIT OCLKFREQ OCLKDUTY Reference clock duty cycle Reference clock frequency tolerance1 Clock output jitter generation with 77.76 MHz reference clock Clock output jitter generation with 155.52 MHz reference clock Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern Frequency output Clock output duty cycle PARAMETER MIN 45 -20 TYP MAX 55 +20 UNITS % ppm mUIrms mUIrms UI 3.5 3.7 0.4 2.488 45 0.7 5.0 5.0 2.667 55 GHz % Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter. 1Required to meet SONET output frequency stability requirements. 2.3 External Signal Detection XRT91L80 supports external Signal Detection (SDEXT). The external Signal Detect function is supported by the SDEXT input. This input is coming from the optical module through an output usually called "SD" or "FLAG" which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The SDEXT and POLARITY inputs are Exclusive OR'ed to generate the external LOSDET signal, internal Loss of Signal Detect (LOSD) declaration and Mute upon LOSD control signal. Whenever an external SD is absent, the XRT91L80 will automatically output a high level signal on the LOSDET output pin as well as update the control registers whenever the host mode serial microprocessor interface feature is active. If LOSDMUTE is enabled, it will force the receive parallel data output to a logic state "0" for the entire duration that a LOSD condition is declared. This acts as a receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming data. Table 4 specifies SDEXT declaration polarity settings. 15 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.1.0 TABLE 4: LOSD DECLARATION POLARITY SETTING SDEXT 0 POLARITY LOSDMUTE 0 1 INTERNAL SIGNAL DETECT Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. CDR PLL LOSDET RXDO[3:0]P/N OUTPUT REFERENCE LOCK Low Normal Operation Hi-Spd Received Data 0 1 1 High LOSD declared High LOSD declared Muted Local Reference Clock 1 0 1 Muted Local Reference Clock 1 1 1 Low Normal Operation Hi-Spd Received Data 2.4 Receive Serial Input to Parallel Output (SIPO) The SIPO is used to convert the 2.488/2.666 Gbps serial data input to 622.08/666.51 Mbps parallel data output which can interface to a SONET Framer/ASIC. The SIPO bit de-interleaves the serial data input into a 4-bit parallel output to RXDO[3:0]P/N. A simplified block diagram is shown in Figure 5. FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO 4-bit Parallel LVDS Data Output RXDO0P/N b03 b02 b01 b00 time (0) 2.488/2.666 Gbps SIPO b33 b23 b13 b03 b32 b22 b12 b02 b31 b21 b11 b01 b30 b20 b10 b00 RXIP/N RXDO1P/N b13 b12 b11 b10 RXDO2P/N b23 b22 b21 b20 RXDO3P/N b33 b32 b31 b30 RXPCLKOP/N 622.08/666.51 MHz 2.5 Receive Parallel Output Interface The 4-bit LVDS 622.08/666.51 Mbps parallel data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered clock. A simplified block diagram is shown in Figure 6. FIGURE 6. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK RXDO0P/N RXDO1P/N RXDO2P/N RXDO3P/N RXPCLKOP/N XRT91L80 STS-48/STM-16 Transceiver SONET Framer/ASIC RXCLKO16P/N SDEXT POLARITY LOSDMUTE DISRD 16 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.6 Receive Parallel Interface LVDS Operation When operating the 4-bit Differential bus in LVDS mode, a 402 external resistor is needed across XRES1P and XRES1N to properly bias the RXDO[3:0]P/N and RXPCLKOP/N pins. Figure 7 shows the proper biasing resistor installed. FIGURE 7. LVDS EXTERNAL BIASING RESISTORS 402 +/- 1 % tolerance pin G1 XRES1P XRES1N pin F1 2.7 Parallel Receive Data Output Mute Upon LOSD The parallel receiver data outputs can be automatically forced "Low" during an LOSD condition to prevent data chattering. However, the user must select the proper SDEXT polarity for the optical module used. By asserting LOSDMUTE "High", the parallel receiver data outputs will be forced "Low" any time an LOSD condition occurs. 2.8 Parallel Receive Data Output Disable Unlike LOSDMUTE, DISRD is used to asynchronously force the parallel receiver data outputs to zero, regardless of the data input stream. By asserting DISRD "High", the parallel receiver data outputs will immediately mute. 2.9 Receive Parallel Data Output Timing The receive parallel data output from the STS-48/STM-16 receiver will adhere to the setup and hold times shown in Figure 8 and Table 5. FIGURE 8. RECEIVE PARALLEL OUTPUT TIMING RXPCLKOP/N tRX_INV RXDO[3:0]P/N tRX_DEL tRXPCLKO tRX_INV SAMPLE WINDOW tRX_DEL TABLE 5: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS SYMBOL tRXPCLKO tRXPCLKO tRX_INV tRX_DEL RXDUTY PARAMETER Receive parallel clock output period (622.08 MHz non-FEC rate) Receive parallel clock output period (666.51 MHz FEC rate) RXPCLKOP/N "High" to data invalid window RXPCLKOP/N "High" to data delay RXPCLKOP/N Duty Cycle 45 MIN TYP 1608 1500 200 200 55 MAX UNITS ps ps ps ps % 17 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION xr REV. P1.1.0 The transmit section of the XRT91L80 accepts 4-bit parallel LVDS data and converts it to serial CML data output intented to interface to an optical module. It consists of a 4-bit parallel LVDS interface, a 4x9 FIFO, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current Mode Logic (CML) differential line driver, and Loop Timing modes. The CML serial data output rate is 2.488/2.666 Gbps for STS-48/STM-16 applications. The high frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In order to synchronize the data transfer process, the synthesized 2.488/2.666 GHz serial clock output is divided by four and the 622.08/666.51 MHz clock is presented to the upstream device to be used as its timing source. 3.1 Transmit Parallel Input Interface The parallel data from an upstream device is presented to the XRT91L80 through a 4-bit LVDS parallel bus interface TXDI[3:0]P/N. The data is latched into a parallel input register on the rising edge of TXPCLKIP/N. If the SONET Framer/ASIC is synchronized to the same timing source as the XRT91L80, the transmit data and clock input can directly interface to the STS-48/STM-16 transceiver. However, if the SONET Framer/ASIC is synchronized to a separate crystal, the XRT91L80 has two clock output references that can be used to synchronize the SONET Framer/ASIC. TXPCLKOP/N is a 622.08/666.51 MHz LVDS clock output source that is derived from the CMU synthesized high-speed clock. TXCLKO16P/N is a 155.52/166.63 MHz LVDS auxiliary clock output source that is also derived from the CMU synthesized high-speed clock. Either of these two clock output sources can be used to synchronize the SONET Framer/ASIC to the XRT91L80. If the auxiliary clock source is not used, it can be disabled by pulling TXCLKO16DIS "High". A simplified block diagram of the parallel interface is shown in Figure 9. FIGURE 9. TRANSMIT PARALLEL INPUT INTERFACE BLOCK TXDI0P/N TXDI1P/N TXDI2P/N TXDI3P/N TXPCLKIP/N XRT91L80 STS-48/STM-16 Transceiver TXPCLKOP/N SONET Framer/ASIC TXCLKO16P/N TXCLKO16DISP/N 18 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 10 and Table 6. FIGURE 10. TRANSMIT PARALLEL INPUT TIMING TXPCLKOP/N tTXPCLKO TXPCLKIP/N tTXDI_SU TXDI[15:0]P/N tTXDI_HD tTXPCLKI TABLE 6: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION SYMBOL tTXPCLKI tTXPCLKI tTXDI_SU tTXDI_HD TXDUTY PARAMETER Transmit parallel clock input period (622.08 MHz non-FEC rate) Transmit parallel clock input period (666.51 MHz FEC rate) TXPCLKIP/N "High" to data setup time TXPCLKIP/N "High" to data hold time TXPCLKIP/N Duty Cycle MIN TYP 1608 1500 MAX UNITS ps ps ps ps 300 300 40 60 % TABLE 7: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION SYMBOL tTXPCLKO tTXPCLKO TXDUTY PARAMETER Transmit parallel clock output period (622.08 MHz non-FEC rate) Transmit parallel clock output period (666.51 MHz FEC rate) TXPCLKOP/N Duty Cycle MIN TYP 1608 1500 MAX UNITS ps ps 45 55 % 3.3 Transmit FIFO The parallel interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed clock. Should the delay exceed this amount, the read and write pointers will point to the same Nibble in the FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET signal. The device under the control of the FIFO_AUTORST pin can automatically recover from an overflow condition. When the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the 19 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.1.0 device will set the OVERFLOW pin to a "High" level and will automatically reset and center the FIFO. Figure 11 provides a detailed overview of the transmit FIFO in a system interface. FIGURE 11. TRANSMIT FIFO AND SYSTEM INTERFACE Upstream Device AUTORST OVERFLOW RESET delay XRT91L80 4 x 9 FIFO TXPCLKIP/N Write Pointer TXDI[3:0]P/N 4 Read Pointer TXPCLKOP/N 4 FIFO Control Div by 4 REFCLKP/N 2.488/2.666 GHz PLL CMU 3.4 FIFO Calibration Upon Power Up It is required that the FIFO_RST pin be pulled "High" for 2 TXPCLKOP/N cycles to flush out the FIFO after the device is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually reset the FIFO. However, the STS-48/STM-16 transceiver has an automatic reset pin that will allow the FIFO to automatically reset upon an Overflow condition. FIFO_AUTORST should be pulled "High" to enable the automatic FIFO reset function. 3.5 Transmit Parallel Input to Serial Output (PISO) The PISO is used to convert 622.08/666.51 MHz parallel data input to 2.488/2.666 Gbps serial data output which can interface to an optical module. The PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI3P/N, then the first bit from TXDI2P/N, and so on as shown in Figure 12. FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF PISO 4-bit Parallel LVDS Data Input TXDI0P/N b07 b06 b05 b04 b03 b02 b01 b00 time (0) TXDI1P/N b17 b16 b15 b14 b13 b12 b11 b10 2.488/2.666 Gbps PISO b30 b20 b10 b00 b31 b21 b11 b01 b32 b22 b12 b02 b33 b23 b13 b03 TXOP/N TXDI2P/N b27 b26 b25 b24 b23 b22 b21 b20 TXDI3P/N b37 b36 b35 b34 b33 b32 b31 b30 TXPCLKIP/N 622.08/666.51 MHz 20 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.6 Clock Multiplier Unit (CMU) and Re-Timer The high-speed serial clock synthesized by the CMU is divided by 4, and is presented to the upstream device as TXPCLKOP/N clock . The upstream device should use TXPCLKOP/N as its timing source. The upstream device then generates the TXPCLKIP/N clock that is phase aligned with the transmit data and provides it to the parallel interface of the transmitter. The data must meet setup and hold times with respect to TXPCLKIP/N. The XRT91L80 will latch TXDI[3:0]P/N on the rising edge of TXPCLKIP/N. The clock synthesizer uses a PLL to lock to the differential input reference clock REFCLKP/N. It will then use this reference clock to generate the 2.488/2.666 GHz STS-48/STM-16 serial clock and in addition feed this high-speed synthesized clock to the PISO. The Retimer will then align the transmit serial data from the PISO with this 2.488/2.666 GHz synthesized clock to generate the output TXOP/N. REFCLKP/N input can accept a clock from a differential LVPECL crystal oscillator that has a frequency accuracy better than 20ppm in order for the high-speed transmit serial clock frequency to have the accuracy required for SONET systems. Table 8 specifies the Clock Multiplier Unit performance characteristics. The CMU can also be driven by an optional external VCXO for loop timed or local reference de-jitter applications. VCXO_INP/N can be connected to the output of a VCXO that can be configured to clean up the recovered received clock coming from CP_OUT in loop timing mode before being applied to the input of the transmit CMU as a reference clock. In addition, the internal phase/frequency detector and charge pump, combined with an external VCXO can alternately be used as a jitter attenuator to de-jitter a noisy system reference clock such as REFCLKP/N prior to it being used to time the CMU. The following Section 3.7, "Loop Timing and Clock Control," on page 21 illustrate the use of this method. TABLE 8: CLOCK MULTIPLIER UNIT PERFORMANCE NAME REFDUTY REFTOL REFSTS48 OCLKJIT OCLKJIT OCLKFREQ OCLKDUTY PARAMETER Reference clock duty cycle Reference clock frequency tolerance1 Reference clock jitter limits from 12 KHz to 20 MHz Clock output jitter generation with 77.76 MHz reference clock Clock output jitter generation with 155.52 MHz reference clock Frequency output Clock output duty cycle MIN 45 -20 TYP MAX 55 +20 -61 UNITS % ppm dBC mUIrms mUIrms GHz % 3.1 2.5 2.488 45 4.0 3.0 2.667 55 Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter. 1 Required to meet SONET output frequency stability requirements. 3.7 Loop Timing and Clock Control Two types of loop timing are possible in the XRT91L80. In the regular loop timing mode (without an external VCXO), loop timing is controlled by the LOOPTM_NOJA pin. This mode is selected by asserting the LOOPTM_NOJA signal to a "High" level. When the loop timing mode is activated, the external local reference clock to the input of the CMU is replaced with the 1/16th or the 1/32nd of the high-speed recovered receive clock coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the recovered receive clock. The normal looptime mode directly locks the CMU to the recovered receive clock with no external de-jittering. Loop timing performance can be further improved using an external VCXO-based PLL to clean up the jitter of the recovered receive clock. In this case the VCXO_SEL pin should be set "High." By doing so, the CMU receives its reference clock signal from an external VCXO connected to the VCXO_INP/N inputs. The LOOPTM_JA pin must also be set "High" in order to select the recovered receive clock as the reference source for the de-jitter PLL. In this state, the VCXO will be phase locked to the recovered receive clock through a narrowband loop filter. The use of the on-chip phase/frequency detector with charge pump and an external VCXO to remove the transmit jitter due to jitter in the recovered clock is shown in Figure 13. 21 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.1.0 The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that is applied to the REFCLKP/N inputs. In this case, the LOOPTM_NOJA pin should be set "Low", the VCXO_SEL set "High", and the LOOPTM_JA pin set "Low". In this configuration, the REFCLKP/N signal is used as the reference to the de-jitter PLL and the de-jittered output of the phase locked VCXO is used as the timing reference to the CMU. Table 9 provides configuration for selecting the loop timing and reference de-jitter modes. TABLE 9: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS VCXO_SEL 0 0 1 1 LOOPTM_JA 0 0 0 1 LOOPTM_NOJA 0 1 0 0 ACTION Normal mode Loop timing without de-jitter VCXO REFCLKP/N reference de-jitter VCXO Loop timing with de-jitter VCXO FIGURE 13. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO VCXO Loop Filter LOOPTM_NOJA LOOPTM_JA VCXO_SEL 0 MUX Phase Detect Charge Pump CPOUT 1 REFCLKP REFCLKN MUX VCXO_INP VCXO_INN 0 1 MUX 0 2.488/2.666GHz CMU PISO 2.488/2.666GHz Retimer TXOP TXON 1 LOCKDET_CMU VCXO_LOCK Div by 16 or 32 ALTFREQSEL Clk CDR Data RXIP RXIN ~ XRT91L80 ~ 22 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.8 External Loop Filter As shown in Figure 13, there is an internal charge pump used to drive an external loop filter and external VCXO. The charge pump current is fixed at 250uA. Figure 14 is a simplified block diagram of the external loop filter and recommended values. FIGURE 14. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER CPOUT VCXO 4.02k 300pF 1uF 3.9 Transmit Serial Output Control The 2.488/2.666 Gbps transmit serial output is avaliable on TXOP/N pins. The transmit serial output can be AC or DC coupled to an optical module or electrical interface. A simplified AC coupling block diagram is shown in Figure 15. FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK 0.1F TXOP TXON 0.1F XRT91L80 STS-48/ STM-16 Transceiver Optical Module Optical Fiber NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors are not necessary and can be excluded. 23 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback xr REV. P1.1.0 The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at the high-speed transmit output TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to parallel data and presented at the low-speed receive parallel interface RXDO[3:0]P/N. The recovered receive clock is also divided by 4 and presented at the low-speed clock output RXPCLKOP/N to synchronize the transfer of the 4-bit received parallel data. A simplified block diagram of serial remote loopback is shown in Figure 16. FIGURE 16. SERIAL REMOTE LOOPBACK Serial Remote Loopback CML Output Drivers FIFO PISO Re-Timer TX Serial Output RX Parallel Output SIPO CDR CML Input Drivers RX Serial Input 4.2 Parallel Remote Loopback RLOOPP controls a more comprehensive version of remote loop-back that can also be used in conjunction with the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is processed by the CDR, and is sent through the serial to parallel converter. At this point, the 4-bit parallel data and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also employed, the received clock is divided down in frequency and presented to the input of the integrated phase/ frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_INP/N inputs. With the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL asserted, the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime the transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset using FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified block diagram of parallel remote loopback is shown in Figure 17. FIGURE 17. PARALLEL REMOTE LOOPBACK Parallel Remote Loopback CML Output Drivers FIFO PISO Re-Timer TX Serial Output RX Parallel Output SIPO CDR CML Input Drivers RX Serial Input 24 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.3 Digital Local Loopback The digital local loopback is activated when the DLOOP signal is set "High." When digital local loopback is activated, the high-speed data from the output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. The CMU output is also looped back to the receive section and is used to synchronize the transfer of the data through the receiver. In Digital loopback mode, the transmit data from the transmit parallel interface TXDI[3:0]P/N is serialized and presented to the high-speed transmit output TXOP/N using the high-speed 2.488/2.666 GHz transmit clock which is generated from the clock multiplier unit and presented to the input of the Retimer and SIPO. A simplified block diagram of digital loopback is shown in Figure 18. FIGURE 18. DIGITAL LOOPBACK Digital Loopback CML Output Drivers TX Parallel Input FIFO PISO Re-Timer TX Serial Output RX Parallel Output SIPO CDR CML Input Drivers 25 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.4 SONET Jitter Requirements xr REV. P1.1.0 SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are specified for the following three types of jitter. 4.4.1 Jitter Tolerance: Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input OC-N equipment interface that causes an equivalent 1dB optical power penalty. OC-1/STS-1, OC-3/STS-3, OC-12/ STS-12 and OC-48/STS-48 category II SONET interfaces should tolerate, the input jitter applied according to the mask of Figure 19, with the corresponding parameters specified in the figure. FIGURE 19. JITTER TOLERANCE MASK A3 slope= -20dB/decade Input Jitter Amplitude (UIpp) slope= -20dB/decade A2 A1 f0 f1 f2 f3 f4 Jitter Frequency (Hz) OC-N/STS-N LEVEL 1 3 12 48 F0 (HZ) 10 10 10 10 F1 (HZ) 30 30 30 600 F2 (HZ) 300 300 300 6000 F3 (HZ) 2K 6.5K 25K 100K F4 (HZ) 20K 65K 250K 1000K A1 (UIPP) 0.15 0.15 0.15 0.15 A2 (UIPP) 1.5 1.5 1.5 1.5 A3 (UIPP) 15 15 15 15 26 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER FIGURE 20. 91L80 MEASURED JITTER TOLERANCE WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS-48. 4.4.2 Jitter Transfer Jitter transfer is defined as the ratio of the jitter on the output of STS-N to the jitter applied on the input of STS-N versus frequency. Jitter transfer is important in applications where the system is utilized in the looptimed mode, where the recovered clock is used as the source of the transmit clock. FIGURE 21. 91L80 MEASURED JITTER TRANSFER WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 GBPS IN STS-48. 27 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.4.3 Jitter Generation xr REV. P1.1.0 Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The Bellcore and ITU requirement for this type jitter is 0.01UI rms measured with a specific band-pass filter. FIGURE 22. 91L80 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS Wide-band filter used in this test case. P h a se N o i se T r a n sm i t J i tte r G e n e r a ti o n (W i d e B a n d ) u si n g H P 8 5 6 0 E -8 5 -9 0 -9 5 -1 0 0 dB C/Hz -1 0 5 -1 1 0 -1 1 5 -1 2 0 -1 2 5 -1 3 0 -1 3 5 1 10 100 F r e q u e n c y (k H z ) R E F C L K = 1 5 5 .5 2 M H z R E F C L K = 7 7 .7 6 M H z 1000 10000 100000 FIGURE 23. 91L80 MEASURED ELECTRICAL PHASE NOISE RECEIVE JITTER GENERATION AT 2.488 GBPS Wide-band filter used in this test case. P h a se N o i se R e c e i v e J i tte r G e n e r a ti o n (W i d e B a n d ) u si n g H P 8 5 6 0 E -8 5 -9 0 -9 5 -1 0 0 dB C/Hz -1 0 5 -1 1 0 -1 1 5 -1 2 0 -1 2 5 -1 3 0 -1 3 5 1 10 100 F r e q u e n c y (k H z ) R E F C L K = 1 5 5.5 2 M H z R E F C LK = 77.76 M H z 1000 10000 100000 For more information on these specifications refer to Bellcore TR-NWT-000253 sections 5.6.2-5 and GR-253CORE section 5.6. 28 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the transceiver. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by pulling reset "Low" for more than 10ms. A simplified block diagram of the Serial Microprocessor is shown in Figure 24. FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE CS SCLK SDI SDO INT Serial Microprocessor Interface HW/Host RESET 5.1 SERIAL TIMING INFORMATION The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 25. FIGURE 25. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE CS 25nS 50nS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SDI R/W A0 A1 A2 A3 A4 A5 X D0 D1 D2 D3 D4 D5 D6 D7 SDO High-Z D0 D1 D2 D3 D4 D5 D6 D7 High-Z NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active "Low") must be de-asserted at the end of every single write or single read operation. 29 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 5.2 16-BIT SERIAL DATA INPUT DESCRITPTION xr REV. P1.1.0 The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is updated on the falling edge of SCLK. The serial data must be applied to the transceiver LSB first. The 16 bits of serial data are described below. 5.2.1 R/W (SCLK1) The first serial bit applied to the transceiver informs the microprocessor that a Read or Write operation is desired. If the R/W bit is set to "0", the microprocessor is configured for a Write operation. If the R/W bit is set to "1", the microprocessor is configured for a Read operation. 5.2.2 A[5:0] (SCLK2 - SCLK7) The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0 (LSB) must be sent to the transceiver first followed by A1 and so forth until all 6 address bits have been sampled by SCLK. 5.2.3 X (Dummy Bit SCLK8) The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data if the readback mode is selected by setting R/W = "1". Therefore, the state of this bit is ignored and can hold either "0" or "1" during both Read and Write operations. 5.2.4 D[7:0] (SCLK9 - SCLK16) The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the address bits. D0 (LSB) must be sent to the transceiver first followed by D1 and so forth until all 8 data bits have been sampled by SCLK. Once 16 SCLK cycles have been complete, the transceiver holds the data until CS is pulled "High" whereby, the serial microprocessor latches the data into the selected internal register. 5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to "1". D0 (LSB) is provided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The SDO pin allows the user to read the contents stored in individual registers by providing the desired address on the SDI pin during the Read cycle. 30 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 10: MICROPROCESSOR REGISTER MAP 6.0 REGISTER MAP AND BIT DESCRIPTIONS REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 Channel 0 Control Register (0x00h - 0x05h) 0 1 2 3 0x00 0x01 0x02 0x03 R/W RUR RO R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved ALTFREQSEL Reserved Reserved Reserved Reserved VCXOIE VCXOIS VCXOD LOOPBW LOSIE LOSIS LOSD VCXO_SEL CDRIE CDRIS CDRD CMUIE CMUIS CMUD FIFOIE FIFOIS FIFOD FIFORST TXCLK016DIS FIFO_AUTORST DISRD Reserved 4 0x04 R/W Reserved POLARITY LOOPTM_ JA Reserved LOOPTM_ NOJA Reserved LOSDMUTE VCXOLKEN 5 0x05 R/W R/W RO RO Reserved Reserved Reserved DLOOP RLOOPS RLOOPP 0x06 - 0x3D 62 63 0x3E 0x3F Reserved Device ID (See Bit Description) Revision ID (See Bit Description) TABLE 11: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION INTERRUPT ENABLE CONTROL REGISTER (0X00H) Register Type Default Value (HW reset) X X X 0 BIT NAME FUNCTION D7 D6 D5 D4 Reserved Reserved Reserved VCXOIE This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used X X X R/W Voltage Controlled External Oscillator Lock Interrupt Enable "0" = Masks the VCXO Lock interrupt generation "1" = Enables Interrupt generation NOTE: VCXOLKEN must be enabled for this bit to have functional meaning. D3 LOSIE Loss of Signal Interrupt Enable "0" = Masks the LOS interrupt generation "1" = Enables Interrupt generation Clock and Data Recovery Lock Interrupt Enable "0" = Masks the CDR Lock interrupt generation "1" = Enables Interrupt generation Clock Multiplier Unit Lock Interrupt Enable "0" = Masks the CMU Lock interrupt generation "1" = Enables Interrupt generation FIFO Overflow Interrupt Enable "0" = Masks the FIFO Overflow interrupt generation "1" = Enables Interrupt generation R/W 0 D2 CDRIE R/W 0 D1 CMUIE R/W 0 D0 FIFOIE R/W 0 31 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 12: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION INTERRUPT STATUS CONTROL REGISTER (0X01H) xr REV. P1.1.0 BIT NAME FUNCTION Register Type Default Value (HW reset) X X X 0 D7 D6 D5 D4 Reserved Reserved Reserved VCXOIS This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used X X X RUR Voltage Controlled External Oscillator Lock Interrupt Status An external interrupt will not occur unless the VCXOIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in VCXO Lock Status Occurred NOTE: VCXOLKEN must be enabled for this bit to have functional meaning. D3 LOSIS Loss of Signal Interrupt Status An external interrupt will not occur unless the RLOSIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in LOS Status Occurred Clock and Data Recovery Lock Interrupt Status An external interrupt will not occur unless the CDRIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in CDR Lock Status Occurred Clock Multiplier Unit Lock Interrupt Status An external interrupt will not occur unless the CMUIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in CMU Lock Status Occurred FIFO Overflow Interrupt Status An external interrupt will not occur unless the FIFOIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in FIFO Overflow Status Occurred RUR 0 D2 CDRIS RUR 0 D1 CMUIS RUR 0 D0 FIFOIS RUR 0 TABLE 13: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION STATUS CONTROL REGISTER (0X02H) Register Type Default Value (HW reset) X X BIT NAME FUNCTION D7 D6 Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used X X 32 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER STATUS CONTROL REGISTER (0X02H) Register Type Default Value (HW reset) X 0 BIT NAME FUNCTION D5 D4 Reserved VCXOD This Register Bit is Not Used X RO Voltage Controlled External Oscillator Lock Detection The VCXOD is used to indicate whether the internal clock reference is locked to an external VCO. "0" = VCXO currently not Locked "1" = VCXO Locked NOTE: VCXOLKEN must be enabled for this bit to have functional meaning. D3 LOSD Loss of Signal Detection The LOSD indicates the LOS activity. "0" = No Alarm "1" = A LOS condition is present Clock and Data Recovery Lock Detection The CDRD is used to indicate that the CDR is locked. "0" = CDR Out of Lock "1" = CDR Locked Clock Multiplier Unit Lock Detection The CMUD is used to indicate that the CMU is locked. "0" = CMU Out of Lock "1" = CMU Locked FIFO Overflow Detection The FIFOD indicates that the FIFO is experiencing an overflow condition. "0" = No Alarm "1" = A FIFO Overflow condition is present RO 0 D2 CDRD RO 0 D1 CMUD RO 0 D0 FIFOD RO 0 TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION CONFIGURATION 0 CONTROL REGISTER (0X03H) Register Type Default Value (HW reset) 0 1 BIT NAME FUNCTION D7 D6 Reserved ALTFREQSEL Reserved - Set to 0 R/W R/W Input Reference Frequency Select This bit is used to select the clock input reference. "0" = 77.76/83.3 MHz "1"= 155.52/166 MHz Reserved - Set to 0 D5 Reserved R/W 0 33 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION CONFIGURATION 0 CONTROL REGISTER (0X03H) xr REV. P1.1.0 BIT NAME FUNCTION Register Type Default Value (HW reset) 0 D4 LOOPBW CMU Loop Band Width Select This bit is used to select the bandwidth of the clock multiplier unit of the transmit path to a narrow or wide band. Use Wide Band for clean reference signals and Narrow Band for noisy references. "0" = Wide Band (4x) "1" = Narrow Band (1x) VCXO De-Jitter Select This bit selects either the normal REFCLKP/N or the de-jitter VCXO_INP/N as a reference clock. "0" = Normal REFCLKP/N Mode "1" = De-Jitter VCXO Mode R/W D3 VCXO_SEL R/W 0 D2 TXCLKO16DIS Auxiliary Clock Disable This bit is used to control the activity of the auxiliary clock. "0" = TXCLKO16P/N Enabled "1" = TXCLKO16P/N Disabled FIFO_ AUTORST R/W 0 D1 Automatic FIFO Overflow Reset If this bit is set to "1", the STS-48/STM-16 transceiver will automatically flush the FIFO upon an overflow condition. Upon power-up, the FIFO should be manually reset by setting FIFO_RST to "1" for a minimum of 2 TXPCLKOP/N cycles. "0" = Manual FIFO reset required for Overflow Conditions "1" = Automatically resets FIFO upon Overflow Detection Manual FIFO Reset FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N cycles after powering up and during manual FIFO reset. After the FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an interrupt indication that the FIFO has an overflow condition, this bit is used to reset or flush out the FIFO. "0" = Normal Operation "1" = Manual FIFO Reset NOTE: To automatically reset the FIFO, see the FIFO_AUTORST bit. R/W 0 D0 FIFO_RST R/W 0 34 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 15: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION CONFIGURATION 1 CONTROL REGISTER (0X04H) Register Type Default Value (HW reset) X 0 BIT NAME FUNCTION D7 D6 Reserved POLARITY This Register Bit is Not Used X R/W Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "0" = SDEXT is active "Low" "1" = SDEXT is active "High" D5 LOOPTM_JA Loop Timing With Jitter Attenuation The LOOPTM_JA bit must be set to "1" in order to select the recovered receive clock as the reference source for the de-jitter PLL. "0" = Disabled "1" = Loop timing with de-jitter PLL Activated R/W 0 D4 LOOPTM_ NOJA Loop Timing With No Jitter Attenuation When the loop timing mode is activated, the external local reference clock input to the CMU is replaced with the 1/16th or 1/32nd of the high-speed recovered receive clock coming from the CDR. "0" = Disabled "1" = Loop timing Activated R/W 0 D3 LOSDMUTE Parallel Receive Data Output Mute Upon LOSD If this bit is set to "1", the receive data output will automatically be forced to a logic state of "0" when an LOSD condition occurs. "0" = Disabled "1" = Mute RXDO[3:0]P/N Data Upon LOSD Condition Parallel Receive Data Output Disable This bit is used to disable the RXDO[3:0]P/N parallel receive data output bus asynchronously. "0" = Normal Mode "1" = Forces RXDO[3:0]P/N to a logic state "0" Reserved - Set to 0 R/W 0 D2 DISRD R/W 0 D1 D0 Reserved VCXOLKEN R/W R/W 0 0 De-Jitter PLL Lock Detect Enable This bit enables the VCXO_INP/N lock detect circuit to be active. "0" = VCXO Lock Detect Disabled "1" = VCXO Lock Detect Enabled TABLE 16: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION DIAGNOSTIC CONTROL REGISTER (0X05H) Register Type Default Value (HW reset) X X BIT NAME FUNCTION D7 D6 Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used X X 35 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER DIAGNOSTIC CONTROL REGISTER (0X05H) xr REV. P1.1.0 BIT NAME FUNCTION Register Type Default Value (HW reset) X X X 0 D5 D4 D3 D2 Reserved Reserved Reserved DLOOP This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used X X X R/W Digital Local Loopback Digital local loopback allows the transmit input pins to be looped back to the receive output pins for local diagnostics. The transmit serial data output is valid during the digital loopback. "0" = Disabled "1" = Enable Digital Local Loopback NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature. Serial Remote Loopback Serial remote loopback allows the receive serial input pins to be looped back to the transmit serial output pins for remote diagnostics. The receive data output is valid during a serial remote loopback. "0" = Disabled "1" = Enable Remote Serial Loopback NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature. D1 RLOOPS R/W 0 D0 RLOOPP Parallel Remote Loopback Parallel remote loopback has the same affect as the serial remote loopback, except that the data input is allowed to pass through the SIPO before it's looped back to the transmit path, wherein it passes through the transmit FIFO, through the PISO, and back out the transmit serial output. The receive data output is valid during a parallel remote loopback. "0" = Disabled "1" = Enable Remote Parallel Loopback NOTE: DLOOP and RLOOPS should be disabled when RLOOPP is enabled. The internal FIFO should also be flushed using FIFO_RST when parallel remote loopback is enabled/ disabled. R/W 0 36 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 17: MICROPROCESSOR REGISTER 0X3EH BIT DESCRIPTION DEVICE "ID" REGISTER (0X3EH) Register Type Default Value (HW reset) 1 1 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Device "ID" The device "ID" of the XRT91L80 LIU is 0xC0h. Along with the revision "ID", the device "ID" is used to enable software to identify the silicon adding flexibility for system control and debug. RO TABLE 18: MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION REVISION "ID" REGISTER (0X3FH) Register Type Default Value (HW reset) This byte shows the revision of the device. BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" The revision "ID" of the XRT91L80 LIU is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon (Revision A) will be 0x01h. RO 37 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 7.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of STBGA Package....jA = 44C/W Thermal Resistance of STBGA Package....jC = 12C/W ESD Protection (HBM)..........................................>2000V xr REV. P1.1.0 Operating Temperature Range.................-40 t o 85 C C Case Temperature under bias..................-55 to 125 C C Storage Temperature ...............................-65 to 150 C C ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS SYMBOL VDD1.8 AVDD1.8 VDD_IO AVDD_IO LVPECL LVDS LVTTL/ LVCMOS LVDS LVCMOS LVPECL LVDS LVTTL/ LVCMOS TYPE PARAMETER 1.8V Digital Core Power Supplies 1.8V Analog Core Power Supplies 3.3V Digital I/O and Power Supply 3.3V Analog I/O and Power Supply DC logic signal input voltage DC logic signal input voltage DC logic signal input voltage MIN -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 TYP MAX 3.6 3.6 6.0 6.0 VDD_IO +0.5 VDD_IO +0.5 5.5 UNITS V V V V V V V DC logic signal output voltage DC logic signal output voltage Input current Input current Input current -0.5 -0.5 -100 -100 -100 VDD_O +0.5 VDD_O +0.5 100 100 100 V V mA mA mA NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods will severely affect device reliability. POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS SYMBOL VDD1.8 AVDD1.8_TX AVDD1.8_RX VDD3.3 TYPE PARAMETER CML and CMOS Core Power Supply Voltage Analog Transmit CML and LVDS Power Supply Voltage (AVDD1.8_TX) Analog Receive CML and LVDS Power Supply Voltage (AVDD1.8_RX) LVPECL and Digital I/O Power Supply Voltage MIN 1.710 1.710 1.710 3.135 TYP 1.8 1.8 1.8 3.3 MAX 1.890 1.890 1.890 3.465 UNITS V V V V CONDITIONS 38 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER PARAMETER Analog Transmit I/O Power Supply Voltage (AVDD3.3_TX) Analog Receive I/O Power Supply Voltage (AVDD3.3_RX) 1.8V Total Power Supply Current 3.3V Total Power Supply Current Total Power Dissipation POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS SYMBOL AVDD3.3_TX AVDD3.3_RX IDD_1.8 IDD_IO PLVDS TYPE MIN 3.135 3.135 TYP 3.3 3.3 262 5 490 MAX 3.465 3.465 UNITS V V mA mA CONDITIONS 650 mW LVDS Mode COMMON MODE LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified SYMBOL VODIFF VIDIFF VISINGLE VIBIAS RDIFF TYPE CML CML CML CML CML PARAMETER Output Differential Voltage Input Differential Voltage Input Single-Ended Voltage Swing Input Bias Range (AC Coupled) Input Differential Resistance MIN 800 200 100 1.0 75 TYP MAX 1200 1000 600 1.4 125 UNITS mV mV mV V CONDITIONS Differential Mode. Differential Mode. Differential Mode. Differential Mode. LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified SYMBOL VIH VIL VIDIFF VISINGLE TYPE LVPECL LVPECL LVPECL LVPECL PARAMETER Input High Voltage Input Low Voltage Input Differential Voltage Input Single-Ended Voltage Swing MIN VDD_IO - 1.2 VDD_IO - 2.0 0.4 0.2 TYP MAX VDD_IO - 0.7 VDD_IO - 1.4 2.4 1.2 UNITS V V V V CONDITIONS Differential Differential Differential Mode. Differential Mode. 39 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified SYMBOL VOH VOL VODIFF VOSINGLE VIH VIL VIDIFF VISINGLE xr REV. P1.1.0 TYPE LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS PARAMETER Output High Voltage Output Low Voltage Output Differential Voltage Swing Output Single-Ended Voltage Swing Input High Voltage Input Low Voltage Input Differential Voltage Swing Input Single-Ended Voltage Swing MIN TYP MAX 1480 UNITS mV mV CONDITIONS 100 line - line 100 line - line 100 line - line 100 line - line 1020 250 125 400 200 1400 800 200 100 mV mV mV mV mV mV LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified SYMBOL VOH VOL VIH VIL ILEAK TYPE PARAMETER MIN TYP MAX 2.4 UNITS V V CONDITIONS IOH = -1.0mA IOH = 1.0mA LVCMOS Output High Voltage LVCMOS Output Low Voltage LVTTL/ Input High Voltage LVCMOS LVTTL/ Input Low Voltage LVCMOS LVTTL/ Input Leakage Current LVCMOS LVTTL/ Input Leakage Current with LVCMOS Pull-Up Resistor LVTTL/ Input Leakage Current with LVCMOS Pull-Down Resistor 0.8 0.4 2.0 V V A A A -10 10 VIN = VDD_IO or VIN = 0 VIN = 0 VIN = VDD_IO ILEAK_PU ILEAK_PD 38 52 65 32 43 55 NOTE: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only. 40 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER ORDERING INFORMATION PART NUMBER XRT91L80IB PACKAGE 196 Shrink Thin Ball Grid Array (12.0 mm x 12.0 mm, STBGA) OPERATING TEMPERATURE RANGE -40C to +85C 196 SHRINK THIN BALL GRID ARRAY (12.0 MM X 12.0 MM, STBGA) REV. 1.00 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A1 Feature/Mark A B C D E F G D D1 H J K L M N P D1 D (A1 corner feature is m fger option) Seating Plane b A2 A1 A e Note: The control dimension is in millimeter. INCHES SYMBOL A A1 A2 D D1 b e MIN MAX 0.053 0.067 0.010 0.022 0.033 0.052 0.465 0.480 0.409 BSC 0.018 0.022 0.031 BSC MILLIMETERS MIN MAX 1.35 1.70 0.25 0.55 0.85 1.31 11.80 12.20 10.40 BSC 0.45 0.55 0.80 BSC 41 XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER REVISION HISTORY REVISION # P1.0.0 P1.0.1 P1.0.2 P1.0.3 xr REV. P1.1.0 DATE October 2004 October 2004 October 2004 January 2005 DESCRIPTION 1st release of the XRT91L80 product brief Fixed typos throughout document Fixed typos throughout document Added jitter transfer and tolerance mask test results and phase noise transmit jitter generation results, added CS de-assertion note on section 5.1, fixed register 0x02, 0x04, 0x05 microprocessor bit descriptions, updated pin descriptions, corrected 'falling edge' typo in section 3.6 to 'rising edge', and enhanced receive and transmit interface block diagrams. Remove 'RXSEL' reference on the RXIP/N pin description. Minor edit in receive section 2.0. FIFO_RST corrected for active High in section 3.4. Removed unsupported note for transparent mode FIFO operation in section 3.3. 1.Design change: Renamed DISRD, TRIRXD, and TRITXCLKO16P/N to LOSDMUTE, DISRD, and TXCLKO16DIS respectively. Corrected and redefined pin definitions for LOSDMUTE, DISRD, and TXCLKO16DIS. 2.Renamed LOSEXT, REFFREQSEL, TXCLKIP/N, RXCLKP/N, RXD[3:0]P/N, RXCLK16P/N, LPTIME_JA, LPTIME_NO_JA, RXP/N to SDEXT, ALTFREQSEL, TXPCLKIP/N, RXPCLKOP/N, RXDO[3:0]P/N, RXCLKO16P/N, LOOPTM_JA, LOOPTM_NOJA, XRES1P/N respectively. 3.Updated STBGA pinout names to include above mentioned changes. 4.Corrected LOOPBW and RLOOPP pin descriptions. 5.Corrected RXDO[3:0]P/N description error from 'updated on rising edge' to 'updated on falling edge' of RXPCLKOP/N. 5.Updated and improved all pin list decriptions and formatted table headers. 6.Added JTAG input pin pull-up and pull-down descriptions. 7.Removed unsupported note for transparent mode FIFO operation in section 3.3 and enhanced and corrected FIFO reset operation description. 8.Moved FIFO Figure 11 from sect 3.6 to section 3.3. 9.Corrected Figure 13, "Loop Timing Mode Using an External Cleanup VCXO. 10.Corrected Loopback definition errors in Section 4.0. 11.Significantly enhanced Sec. 2.3 "LOS" to "External Signal Detection, Sec. 3.3 Transmit FIFO, and Sec. 3.6 CMU and Retimer, and Sec. 3.7 Loop timing and Clock Control. 12.Enhanced Transmit/Receive Parallel Data and Clock Input/Output timing diagram and tables. 13.Added CMU and CDR performace tables. 14.Added CML input swing characteristics table. 15.Added LOSD declaration polarity setting tables. 16.Added LVDS biasing resistor diagram. 17.Reformatted and Enhanced AC/DC electrical characteristics tables. 18.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accurately. Corrected and enhanced PISO and SIPO diagrams. 19.Removed all reference to "differential limiting amplifier" and TXO2P/N pins. 20.Updated Microprocessor Register Bits and Descriptions to reflect changes. 21.Added Microprocessor Register Names. 22.Retouched 91L80 Block Diagram. 23.Changed OC-48 name to STS-48. 24.Minor edits and spelling and grammatical corrections. P1.0.4 March 2005 P1.0.5 April 2005 42 xr REV. P1.1.0 PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER DATE July 2005 REVISION HISTORY REVISION # P1.0.6 DESCRIPTION 1.Updated CML input swing characteristics table. 2.Updated CDR and CMU jitter performance parameters. 3.Updated Intrinsic Transmit and Receive Phase Noise performance plots. 4.Updated AC/DC electrical characteristics tables. 1.Revision E silicon: CMOS Digital 1.8V power pins P13 and P14 changed to 3.3V. 2.Revision E silicon: ALTFREQSEL default clock selection changed to 155.52 MHz. P1.1.0 July 2005 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet July 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 43 |
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